Tachyum: 128 Cores at 5.7GHZ with two 1024 bit vector units each(youtube.com)
youtube.com
Tachyum: 128 Cores at 5.7GHZ with two 1024 bit vector units each
https://www.youtube.com/watch?v=siN1eQ0SfxU
11 comments
This analysis from ex-Anandtech Ian Cutress and two contributors to the excellent Chips and Cheese is pretty great for processor architecture fans. See also: https://chipsandcheese.com/2022/08/26/tachyums-revised-prodi...
Designs like this are what I like to see in my field of implicit modeling of geometry. We need processors with more general purpose ISA, recursion, and 64 bit floats due to the functional techniques we use. There's a fair amount of impedence mismatch for that using current triangle pushing GPUs, as sophisticated as they are getting. Thanks for posting!
This is the Moller Skycar of the CPU world. Who cares about the ever changing details after 5+ years of empty hype that make Intel seem conservative? It’ll probably change again too but still the weekly press releases about their new strategic alliance with some falafel place or achievement of emulating their emulator’s Makefile will roll on.
According to the article Rado has sold every company he's founded (and presumably delivered on all of them too) so it would be a first if he didn't at least exit on this one.
I personally have some knowledge here as one of his companies was in my business. Grandiose claims, that if real would have made his company a market leader, but sold off to a desperately naive buyer. In a sense it was a dress rehearsal for Tachyum.
Maybe I’ll be proven wrong in a year, maybe Rado will be on to home fusion reactors after foisting Tachyum’s shell on Intel? ;)
Maybe I’ll be proven wrong in a year, maybe Rado will be on to home fusion reactors after foisting Tachyum’s shell on Intel? ;)
The video doesn’t seem to be made by a bunch of outsiders. They seem skeptical of some of the claims, but in the whole giving Tachyum the benefit of the doubt - but maybe they’re motivated to be a little sensational for the viewers
We can fairly discuss architectures all day. The Mill anyone? I still have no evidence that anything exists here beyond Powerpoint and promises of simulation. Even Elbrus, admittedly after many years, turned hardware.
Edit: does anyone else remember the promises of MicroUnity?
Edit: does anyone else remember the promises of MicroUnity?
> The Mill anyone?
I had the Mills architecture in the back of my mind while watching that video. I wonder what became of the team?
I had the Mills architecture in the back of my mind while watching that video. I wonder what became of the team?
Does nothing well except generate heat.
> Does nothing well except generate heat.
Like the current GPUs running my application?
I wish you would directed that to my comment above. I would reassert that something like this, perhaps with the qualification of it being well engineered and efficient, is what I would like to run my graphics application on--a highly parallelizable algorithm but with need for a general ISA, recursion, and 64 bit floats--and the ability to get rid of CUDA and OpenCL. Given this, do you have any suggestions for something better? And why?
Like the current GPUs running my application?
I wish you would directed that to my comment above. I would reassert that something like this, perhaps with the qualification of it being well engineered and efficient, is what I would like to run my graphics application on--a highly parallelizable algorithm but with need for a general ISA, recursion, and 64 bit floats--and the ability to get rid of CUDA and OpenCL. Given this, do you have any suggestions for something better? And why?
Well obviously the correct answer is to abandon the von Neuman architecture and start processing in memory instead of burning more and more watts.
"Each UPMEM PIM DIMM contains 128 DPUs each communicating at 1GB/s with their 64 MB of memory for a total of 160 GB of PIM memory. The DPU is a 24 threads, 32-bit RISC processor – with 64-bit capabilities – working at 450Mhz (soon 600Mhz). A dual socket cascade lake server totalizes up to 2560 DPUs while the upcoming Ice Lake platform will welcome up to 28 PIM DIMMS, that is 3584 DPUs."
"Each UPMEM PIM DIMM contains 128 DPUs each communicating at 1GB/s with their 64 MB of memory for a total of 160 GB of PIM memory. The DPU is a 24 threads, 32-bit RISC processor – with 64-bit capabilities – working at 450Mhz (soon 600Mhz). A dual socket cascade lake server totalizes up to 2560 DPUs while the upcoming Ice Lake platform will welcome up to 28 PIM DIMMS, that is 3584 DPUs."