Intel announces new FPGA families(fpgaer.tech)
fpgaer.tech
Intel announces new FPGA families
https://fpgaer.tech/?p=561
69 comments
I wonder if the war has anything to do with this actually. These chips and some larger STM32 like F7 and H7 are dual use and can be used in missiles and drones.
I couldn't buy the car manufacturers' excuse. I think MICs around the world have been stockpiling these chips.
Raspberry Pis too. The shortage feels targeted. Or I’m just being an idiot as always.
Pine64 has some pretty nice ARM (and fairly priced) boards that seem to be in stock. Maybe one of those will suffice for your application?
https://pine64.com/product-category/single-board-computers/
https://pine64.com/product-category/single-board-computers/
This is the official statement of the Raspberry Pi Foundation on this topic:
> https://www.raspberrypi.com/news/production-and-supply-chain...
Excerpt:
"As we’ve said before, the current situation is as much a demand shock as a supply shock: demand for Raspberry Pi products increased sharply from the start of 2021 onwards, and supply constraints have prevented us from flexing up to meet this demand, with the result that we now have significant order backlogs for almost all products. In turn, our many resellers have their own backlogs, which they fulfil when they receive stock from us.
These backlogs absorb Raspberry Pi units as fast as (or faster than!) we can produce them, with the result that little of our production volume ends up being immediately available on reseller websites. Where units do appear, bots often attempt to scalp stock which is then resold at higher prices elsewhere."
Different perspectives are given in the answer https://raspberrypi.stackexchange.com/questions/139020/why-i...
In particular, the following alternative explanations are discussed (which don't exclude each other):
- industrial customers are given priority
- there are currently deep changes in the Raspberry Pi Foundation happening
> https://www.raspberrypi.com/news/production-and-supply-chain...
Excerpt:
"As we’ve said before, the current situation is as much a demand shock as a supply shock: demand for Raspberry Pi products increased sharply from the start of 2021 onwards, and supply constraints have prevented us from flexing up to meet this demand, with the result that we now have significant order backlogs for almost all products. In turn, our many resellers have their own backlogs, which they fulfil when they receive stock from us.
These backlogs absorb Raspberry Pi units as fast as (or faster than!) we can produce them, with the result that little of our production volume ends up being immediately available on reseller websites. Where units do appear, bots often attempt to scalp stock which is then resold at higher prices elsewhere."
Different perspectives are given in the answer https://raspberrypi.stackexchange.com/questions/139020/why-i...
In particular, the following alternative explanations are discussed (which don't exclude each other):
- industrial customers are given priority
- there are currently deep changes in the Raspberry Pi Foundation happening
The fact that they are shipping new PCB revisions of their boards with alternative components (like different PMICs) supports the claim that (at least) part of the shortage was due to supply problems.
https://forums.raspberrypi.com/viewtopic.php?t=337023
https://forums.raspberrypi.com/viewtopic.php?t=337023
I was working for a customer (medical) last 12 months with a Zynq design. I remember at the time the distributor specifically saying they were being instructed to give priority to US companies on their stock as it arrived (I assume defense).
They had to have a meeting with higher uppers at the distributor to scramble about 200 pieces industrial grade from them (that was basically a year's worth of production for that product, low volume production).
So I have no doubt that whatever mil contractors need they will get it.
They had to have a meeting with higher uppers at the distributor to scramble about 200 pieces industrial grade from them (that was basically a year's worth of production for that product, low volume production).
So I have no doubt that whatever mil contractors need they will get it.
Situation is dire even for contractors unless your product is already in production and has somebody on the government side advocating for you.
I know the Cyclone V specifically is used in the MiSTer project (https://www.retrorgb.com/mister.html), I'm not sure how big a part of overall demand that is though.
I don't think STM32 MCUs are that special, not are they related to Intel FPGAs. There are plenty of STM32 clones out there and manufacturers have moved on.
Clones of more advanced STM32 don't exist. There is GD32F4xx but it's not as powerful as the originals and I doubt anyone in the right mind would use these where reliability is paramount.
The Intel Direct RF FPGAs are pretty spectacular. They report 64GSPS and 25GHz instantaneous bandwidth directly into FPGA fabric (no JESD) which greatly exceeds any other competitors’ IC offerings on the market. I wonder what they will cost: if their high-end 8ch device is <$16K then they will annihilate the competition (I’m able to get $2K per channel for large multichannel direct RF systems 1Ghz instantaneous all the way up to x-band)
I can only imagine how long it will take the fitter to pnr these insanely wide busses. Maybe a 13th gen CPU overclocked to 8GHz would be handy.
Days at least. P&R is NP hard I believe. Force directed placement or simulated annealing is slow and random :/
Xilinx keeps advertising the bejeesus out of their AI p&r, but I haven't touched these tools in years -- how much do the claims translate to reality?
Considering my experience with Xilinx, the more they advertise it the harder it sucks.
Xilinx design tools are some of the buggiest pieces of software known to humankind. Altera(Intel) not far behind.
This applies to basically all electronics design tools. Insanely expensive ($5-100k per seat per year is common) and insanely buggy.
Altium, considered one of the best PCB cad tools, hard crashes for me every hour or two of design work I do.
Altium, considered one of the best PCB cad tools, hard crashes for me every hour or two of design work I do.
Following Altera acquisition by Intel, and Xilinx acquisition by AMD, perspectives for many FPGA designers were gloom. There was a general feeling that the two biggies would go to a road where the FPGA is only and add-on or coprocessor for CPU workhorses, for applications like Data centers and ML acceleration.
Well, according to these news from Intel, that's not the case. Intle announces new mid-level FPGAs and even new FPGA to compete with Xilinx RFSoCs
Well, according to these news from Intel, that's not the case. Intle announces new mid-level FPGAs and even new FPGA to compete with Xilinx RFSoCs
I share(d) that concern. Mitigating this is that a lot of (low to mid range) alternatives seems to have gotten steam: Lattice Semi, Efinix, Gowin, and more that I forget at the moment. I'm rooting strongly for the underdogs to become viable alternatives to the current duopoly.
It would of course have been preferable for any of them to directly support the open stack (yosys, nextpnr, and the various bitstream generators); Lattice's ECP5 is nice, but not very fast.
It would of course have been preferable for any of them to directly support the open stack (yosys, nextpnr, and the various bitstream generators); Lattice's ECP5 is nice, but not very fast.
My particular worry was that AMD would cancel Xilinx's CPLD chips, but so far it does not look like it. They are very very useful if you want to replace old 74xxx circuits and greatly simplify development.
I see a lot of use of FPGAs in things like cutting-edge machinery, warfare, and stock trading. Are there any cool hobbyist uses of these things? Always game to learn a new tech.
For me, one option is to be able to learn processors in depth. You want to understand how one works? You can always emulate it in SW, but on an FPGA you can make them interact with the real world in real time and probe them at the same time, with ready made signal analyzers that the vendors provide, and/or by making your own tools.
Another option, do you want to see by yourself how caching improves code performance? You can make that on an FPGA also.
I have done some time ago a very nice course which is called From Nand to Tetris, that teaches how to go all the way from gates to a processor. My plan for the near future is to implement the NAND2Tetris processor on a Basys 3 board, and make some of the examples I mentioned (like, probing internal registers using HW tools, or seeing by yourself how a cache improves performance). I hope to make some of these things available on my site. I am the OP, but just in case, my website is https://fpgaer.tech
Another option, do you want to see by yourself how caching improves code performance? You can make that on an FPGA also.
I have done some time ago a very nice course which is called From Nand to Tetris, that teaches how to go all the way from gates to a processor. My plan for the near future is to implement the NAND2Tetris processor on a Basys 3 board, and make some of the examples I mentioned (like, probing internal registers using HW tools, or seeing by yourself how a cache improves performance). I hope to make some of these things available on my site. I am the OP, but just in case, my website is https://fpgaer.tech
There is vast spread of FPGA sizes, so on affordability side it's definitely possible and some people did it.
The "problem" is really that you can do a LOT with MCUs, and programming FPGAs is very different than microcontrollers serially executing your code so they are pretty niche.
Like, if you for example needed to drive few thousand neopixels techncially FPGA would be perfect use case, just make a blob of memory and a bunch of serializers that feed each chain of LEDs.
... or you can just use some DMA magick on some fast STM32 and hack it out without having to learn new programming language.
The "problem" is really that you can do a LOT with MCUs, and programming FPGAs is very different than microcontrollers serially executing your code so they are pretty niche.
Like, if you for example needed to drive few thousand neopixels techncially FPGA would be perfect use case, just make a blob of memory and a bunch of serializers that feed each chain of LEDs.
... or you can just use some DMA magick on some fast STM32 and hack it out without having to learn new programming language.
When would a hobbyist need processing much faster than a modern beefy CPU provides, but not in a highly parallel fashion which a modern GPU provides?
My only relatively reasonable suggestion is making perfect hardware emulators for old hardware, like vintage computers and their parts.
Alas, FPGA programming model is neither easy nor intuitive, and the tools are mostly proprietary, expensive, and (as I heard) have a steep learning curve.
My only relatively reasonable suggestion is making perfect hardware emulators for old hardware, like vintage computers and their parts.
Alas, FPGA programming model is neither easy nor intuitive, and the tools are mostly proprietary, expensive, and (as I heard) have a steep learning curve.
Not just emulators. You can do nifty things, like redirect RAM reads and writes to a different location, save states, freeze the CPU, feed it with a different ROM (bypassing the one in your board), etc.
https://bitfixer.com/2020/02/19/romulator-6502-is-ready/
https://bitfixer.com/2020/02/19/romulator-6502-is-ready/
These things get used in dsp and other radio applications all the time.
>Are there any cool hobbyist uses of these things?
Yes, there is, if you're willing to learn.
>Always game to learn a new tech.
Great. A good starting point is NANDLand[0].
Their board is not at all a bad purchase at <$100, particularly to follow their tutorials, but you can do better[1] if you are adventurous. e.g. iCEBreaker or iCESugar.
I'd still recommend to stick to iCE40 and the open source yosys/nextpnr stack, until you become competent enough to actually know what you want/need.
[0] https://nandland.com/
[1] https://www.joelw.id.au/FPGA/CheapFPGADevelopmentBoards
Yes, there is, if you're willing to learn.
>Always game to learn a new tech.
Great. A good starting point is NANDLand[0].
Their board is not at all a bad purchase at <$100, particularly to follow their tutorials, but you can do better[1] if you are adventurous. e.g. iCEBreaker or iCESugar.
I'd still recommend to stick to iCE40 and the open source yosys/nextpnr stack, until you become competent enough to actually know what you want/need.
[0] https://nandland.com/
[1] https://www.joelw.id.au/FPGA/CheapFPGADevelopmentBoards
For someone making hobby electronics experiments, an FPGA can be used to make a cheap (but with modest performances) logic analyzer and digital oscilloscope (and test signal generator, if desired).
Many years ago, that would have been the only solution to avoid paying thousands of dollars for a professional instrument.
However, nowadays there exist a number of commercial solutions for such cheap instruments, which are made exactly like this, i.e. with an FPGA surrounded by appropriate I/O circuits and connectors, some USB or Ethernet interface for the PC and some capture software.
These have the advantage that are ready to use out of the box, but making yourself such an instrument can be instructive.
Many years ago, that would have been the only solution to avoid paying thousands of dollars for a professional instrument.
However, nowadays there exist a number of commercial solutions for such cheap instruments, which are made exactly like this, i.e. with an FPGA surrounded by appropriate I/O circuits and connectors, some USB or Ethernet interface for the PC and some capture software.
These have the advantage that are ready to use out of the box, but making yourself such an instrument can be instructive.
There's always sound or image generation, or programming a game like Pong. That's always looked cool to me. There are some "easy" entry points, e.g. https://maker.pro/arduino/tutorial/getting-started-with-fpga..., but I've never gone as far as actually try them.
With a bit of luck, someone will reply with better options.
Edit: or look at this list: https://hackaday.io/search?term=fpga
With a bit of luck, someone will reply with better options.
Edit: or look at this list: https://hackaday.io/search?term=fpga
The Cypress PSoC might be of interest. It's a combination FPGA and microcontroller, the low-end demo boards with USB programming get as low as ~$10.
Though most of what you can do with the FPGA would be covered by built-in timer/capture modules or the PICO PIO modules on other chips (though IIRC, some of the boards have analog support in the FPGA if you wanted to do real-time audio processing). I have not found a particular hobbyist use for them, only know it from my father teaching some computer engineering courses and picking since he could use the same board for digital logic and microcontroller programming.
Though most of what you can do with the FPGA would be covered by built-in timer/capture modules or the PICO PIO modules on other chips (though IIRC, some of the boards have analog support in the FPGA if you wanted to do real-time audio processing). I have not found a particular hobbyist use for them, only know it from my father teaching some computer engineering courses and picking since he could use the same board for digital logic and microcontroller programming.
The announcement is surprisingly lacking in architectural updates; it looks like the same Agilex on a new process. Has Intel killed innovation?
ADD: last time I witnessed something actually new and interesting: https://www.efinixinc.com/technology.html
ADD: last time I witnessed something actually new and interesting: https://www.efinixinc.com/technology.html
FPGA innovation is very incremental. The hyperflex architecture is basically the single biggest innovation in FPGA fabric, and it basically didn’t pay off. Altera also smashed up against the wall of Intel 10nm. So all in all, some reduced precision for AI and some EMIB enabled stuff isn’t too bad.
Needs better tools to take advantage of it, right now using hyperflex (registers on long routing lines to automatically pipeline your designs) is quite difficult from what I have heard.
Yeah, this was one of those situations where the hardware guys create a super cool thing that requires amazingly complex software to take advantage, and it turns out the software guys aren't going to solve all the problems you created.
Indeed, that was the downfall of Tabula (sniff)
With a simple, public, open and stable in time hardware programing interface?
I mean not a scam.
I mean not a scam.
Anyone able to give a rough estimate of how much one of the FPGAs with R-Tile would cost per device for a small order (1-5)? 1k, 10k, 100k? Are they likely to be available any time soon?
That's some news because Intel hadn't in a while.
But IMHO this is is far more interesting:
https://hardwarebee.com/gowin-semiconductor-new-22nm-high-pe...
This is a real contender from China. Not just some new cheap chip, but actually competitive with Intel/Lattice/Xilinx offerings.
But IMHO this is is far more interesting:
https://hardwarebee.com/gowin-semiconductor-new-22nm-high-pe...
This is a real contender from China. Not just some new cheap chip, but actually competitive with Intel/Lattice/Xilinx offerings.
Competitive in what sense? in which market outside of china? Cyclone V a decade old platform offers similar capability and is a tested platform.
You can buy their parts on mouser and they have "small" fpgas too
there are even few in stock https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1N...
there are even few in stock https://eu.mouser.com/ProductDetail/GOWIN-Semiconductor/GW1N...
... at 22nm?
Apples to oranges.
Apples to oranges.
Cyclone V is 28nm so it should be outclassed by a new product offering in 2022 thats manufactured at a better node right? i'm not saying its a bad design, but that product is not a competitive offering. this new family from intel is on intel 7 node which is at scale intel can eat node prices to stay competitive. intel will probably price this competitively with its cyclone v offering if that happens intel will eat the market share of xilinx and lattice unless they announce something new.
I'll avoid these chips merely because they don't have support in the Open Source FPGA stack (yosys/nextpnr), whereas other chips do.
FPGAs would be so much more useful if AMD(Xilinx)/Intel(Altera) just gave up trying to build there own tools and instead supported F4FPGA: https://f4pga.org
Note that some vendors actually do. QuickLogic mentioned there was contributed by the company making these FPGAs.
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I want to write an open source FPGA synthesizer so badly.
Is it still very difficult for generic programmers to program an FPGA for their particular application?
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Can someone estimate the power of these new FPGAs? Is a MisterFPGA with n64/PS2 emulation in range?
Yes, but that's not the problem. The problem is these Agilex devices are insane overkill for that task, and you likely won't be able to buy the SKUs in a reasonable form factor or price for that use case. The Mister worked so well because the actual design of the device has the right blend of peripherals/compute and Intel/terASIC ate the NRE to design and manufacture it, and that's because they intended it use it to teach and educate people and needed a lot of volume for that. Agilex isn't a teaching part. It's their most advanced top-of-the-line part with its own logic design requirements that differentiate it from earlier lines (Arria 10 and prior.)
You likely aren't going to see "consumer-oriented" Agilex-powered devices in similar form factors anytime soon; most of the compute power of the fabric would be completely wasted without fast peripherals/storage anyway (the fabric can be clocked very high if you pipeline enough) and the shipping volume to make the boards attractive/low-price enough would need to be pretty decent. This means the board would actually end up expensive; why pay so much for the FPGA if all the I/O sucks? But good I/O is expensive. The Agilex parts are some of Intel's most complex devices on their latest "Intel 7" process too, it's not cheap.
I guess it's maybe something that would be possible to crowdfund in low volumes, but it's a truly huge amount of work even before you get to price. Designing the board, getting the software and tools working, documentation, that's before you even manufacture. And realistically there are probably other FPGA options that would be cheaper and more readily available. Something like a Kintex-7, or Arria 10 part would probably do just as well for significantly cheaper, I'd think, but it's hard to guess unless you have more concrete requirements in terms of LEs/memory/clock speeds.
Maybe if you pray they will make an Agilex-D PCIe developer kit that "only" costs $2k USD, requires tiny fans that sound like jet engines, and has 1 HDMI out.
You likely aren't going to see "consumer-oriented" Agilex-powered devices in similar form factors anytime soon; most of the compute power of the fabric would be completely wasted without fast peripherals/storage anyway (the fabric can be clocked very high if you pipeline enough) and the shipping volume to make the boards attractive/low-price enough would need to be pretty decent. This means the board would actually end up expensive; why pay so much for the FPGA if all the I/O sucks? But good I/O is expensive. The Agilex parts are some of Intel's most complex devices on their latest "Intel 7" process too, it's not cheap.
I guess it's maybe something that would be possible to crowdfund in low volumes, but it's a truly huge amount of work even before you get to price. Designing the board, getting the software and tools working, documentation, that's before you even manufacture. And realistically there are probably other FPGA options that would be cheaper and more readily available. Something like a Kintex-7, or Arria 10 part would probably do just as well for significantly cheaper, I'd think, but it's hard to guess unless you have more concrete requirements in terms of LEs/memory/clock speeds.
Maybe if you pray they will make an Agilex-D PCIe developer kit that "only" costs $2k USD, requires tiny fans that sound like jet engines, and has 1 HDMI out.
You would easily eventually get into volumes of 2-3 million a year if you could get something out which is powerful enough for PS2 level re-creation.
The MiSTER project is already inspiring a generation to learn how to program FPGAs, those skills could be applied to improve performance in a lot of applications.
The MiSTER project is already inspiring a generation to learn how to program FPGAs, those skills could be applied to improve performance in a lot of applications.
I'd like to know how many MiSTer owners there are in the world.
Part of me wants to say it's a lot, and part of me wants to say that the retro gaming community is peanuts compared to other FPGA consumers.
Part of me wants to say it's a lot, and part of me wants to say that the retro gaming community is peanuts compared to other FPGA consumers.
I suspect the same. My view is that the MiSTer FPGA crowd is very loud in the subreddits and discord channels of the world, but in reality most people using FPGAs in any significant capacity are much more tight lipped about it.
Yes, but recreating the PS2 is an order of magnitude more complicated than a PS1, which is still a massive undertaking for an individual. Even supposing we had a cheap enough FPGA, who would write the HDL to simulate a PS2?
The ps1 cpu was just a mips. Building a mips cpu with an fpga is a normal required undergrad project for a cs degree or it was a couple decades ago. I was feeling dismissive until I looked at the specs for the gpu and spu... That was some serious work for the ps1. The ps2 had that odd cell processor, or emotion engine whatever you want to call it. Its still basically multiple simplified mips cores but now all the stuff to synchronize them correctly? I'm surprised the ps2 emulators are as close as they are. Doing it all in hdl, and with the upgraded gpu, that is enough work that I wonder if software emulation fidelity wouldn't reach hardware fidelity before the fpga design did.
PS3 was Cell processor..
PS2 Emotion Engine..
Ah! The ps2 was still like 8 cores right?
I'll try to answer this, though my direct experience is only with Cyclone and Max 10.
The Mister uses the Cyclone V 5CSEBA6U23I7 built on TSMC 28nm. It has 110000 logic elements and also a hard ARM.
These are on Intel 7, so there a significant process improvement.
The smallest Agilex D has the same number of logic elements(1) and the largest has 6x as many (2). Note that Agilex tends to be much more expensive than Cyclone.
Realistic maximum clock rates on the Cyclone V are 50-200MHz, depending on the length of the combinational logic chains. For the Agilex I think that it is more like peak 600MHz. So I would guess say 25% faster and say peak 750MHz?
As to fitting all the logic for n64/PS2, I don't know!
1) Comparing these directly is not quite accurate.
2) https://www.intel.com/content/www/us/en/products/docs/progra...
The Mister uses the Cyclone V 5CSEBA6U23I7 built on TSMC 28nm. It has 110000 logic elements and also a hard ARM.
These are on Intel 7, so there a significant process improvement.
The smallest Agilex D has the same number of logic elements(1) and the largest has 6x as many (2). Note that Agilex tends to be much more expensive than Cyclone.
Realistic maximum clock rates on the Cyclone V are 50-200MHz, depending on the length of the combinational logic chains. For the Agilex I think that it is more like peak 600MHz. So I would guess say 25% faster and say peak 750MHz?
As to fitting all the logic for n64/PS2, I don't know!
1) Comparing these directly is not quite accurate.
2) https://www.intel.com/content/www/us/en/products/docs/progra...
did you really mean 25% faster or 4x faster?
If you really meant 25% you probably were not reffering to the clock speed/MHz, what were referring to?
If you really meant 25% you probably were not reffering to the clock speed/MHz, what were referring to?
I did mean 25% faster, though it was a guesstimate. That was comparing Agilex to Agilex D, not Cyclone V to Agilex D.
FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.
Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.
Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.
I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.
FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.
Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.
Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.
I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.
Would a Xilinx-based equivalent to MiSTer hardware have a better price-to-performance ratio?
Wow thanks.
So for the Agilex D the answer is maybe, since the currently limiting factor seems to be number of logic elements and it would need at least a 3x upgrade in that regard [1] for n64. Well, one can hope that these become cheap enough for that.
[1] https://misterfpga.org/viewtopic.php?t=4535
[1] https://misterfpga.org/viewtopic.php?t=4535
You can in theory clock the Agilex/S10 parts up-to 1GHz, but something like 600-700MHz sounds more realistic, yes. (Note that this is in the same ballpark as what Virtex UltraScale+ can do too.)
Also, regarding point 1 -- and I'm sure you know this already, but this is for everyone else -- you have to be careful when talking about "Logic Elements" with most of the industry because, even when describing 6-LUT parts, Intel/Xilinx often list "Logic Element Count" to mean "Number of logic elements when considered on a normalized 4-LUT basis." Both Intel and Xilinx do this and I guess it kind of makes sense; only their highest end parts are non-4LUTs so they're the odd ones out when compared to everything else in the industry. So when you read "Number of LEs", they normalize it to 4-LUTs since that's what your competitors (or older parts) would use, when accounting for density.
For example I have a Stratix 10 card in my server that has "Millions of logic elements" when you look at the product tables, but that is taken on a normalized 4-LUT basis. There are actually "only" about 900,000 ALMs on the device, with each ALM being 8-input and fracturable. So TL;DR the numbers between the low-end Agilex-D part and the Cyclone part is maybe not that far off.
Also, regarding point 1 -- and I'm sure you know this already, but this is for everyone else -- you have to be careful when talking about "Logic Elements" with most of the industry because, even when describing 6-LUT parts, Intel/Xilinx often list "Logic Element Count" to mean "Number of logic elements when considered on a normalized 4-LUT basis." Both Intel and Xilinx do this and I guess it kind of makes sense; only their highest end parts are non-4LUTs so they're the odd ones out when compared to everything else in the industry. So when you read "Number of LEs", they normalize it to 4-LUTs since that's what your competitors (or older parts) would use, when accounting for density.
For example I have a Stratix 10 card in my server that has "Millions of logic elements" when you look at the product tables, but that is taken on a normalized 4-LUT basis. There are actually "only" about 900,000 ALMs on the device, with each ALM being 8-input and fracturable. So TL;DR the numbers between the low-end Agilex-D part and the Cyclone part is maybe not that far off.
100%. For the record, the metrics I care about, and the first I seek out, is blockram cycle time and total device memory capacity. Unfortunately, unlike say Xilix/AMD, Intel doesn't publish that number directly, but Xilix/AMD's fastest for is > 800 MHz for the lovely Artix US+ and it has loads of memory.
The LUT count is a murky beast beast as you realistically cannot use them all lest P&R times shall be counted in weeks.
The LUT count is a murky beast beast as you realistically cannot use them all lest P&R times shall be counted in weeks.
When you talk about "mid-range" in Intel's current product line up, that usually means the Arria 10 line. Those are typically around $1,000 for just the FPGA package itself, so I don't think we're realistically talking about something that's going to make meaningful impact on the hobbyist emulation market.
I understand there is an ongoing major chip shortage but it has been over 2 years and historically these were available next day. I'm sure that I'm not the only one waiting for years with finished designs and no information.
I asked Digikey and they told me that Intel do not provide them with good communications, such that they cannot even populate this, never mind to provide a lead time per product. https://www.digikey.ch/en/resources/reports/lead-time-trends