Distance-Based ISA for Efficient Register Management(sigarch.org)
sigarch.org
Distance-Based ISA for Efficient Register Management
https://www.sigarch.org/distance-based-isa-for-efficient-register-management/
5 comments
They say that "the distance-based representation is novel", but it seems at least similar to the Mill CPU's belt idea.
The article mentions getting SPEC CPU running but doesn't share performance results or scalability results (now the CPU can decode twice as many instructions, etc). Can someone who has been following the research in this area share some results?
A question, is it distance as in from the PC (absolute addressing from a datum) or as in the number of instructions executed (meaning a 4 byte conditional branch can shift the whole history)?
It's more or less a ring buffer - new results are pushed on one by one, old results get popped off by being overwritten, and distances are relative to the newest entry.
Their second design, "clockhands", has multiple ring buffers, which makes it much easier to deal with conditional branches, amongst other things. Their third, "turbulence" has both a ring buffer and conventional registers.
Their second design, "clockhands", has multiple ring buffers, which makes it much easier to deal with conditional branches, amongst other things. Their third, "turbulence" has both a ring buffer and conventional registers.
EDIT: Derp! RIP-relative x64? I've not coded x64 in 15 years, so I don't remember how pervasive the addressing mode is.
I guess the author's are trying to explore a ground-up implementation? Maybe the uarch is really exotic?