Interesting but not new. Back in 2005 I implemented a random syntax forest walker that generates random Verilog/VHDL test cases. My colleague extended the tool so it compares simulation results with other simulators. This became part of Altera (acquired by intel in 2015) Quartus II code base.
On the first day we generated 10k test cases, found ~1k failures and they boiled down to ~20 bugs.