dspwizard · HackerTrans

5 เดือนที่ผ่านมาdiscuss

VLIW works great when you have predictable & short latencies of memory accesses - you will not find DSP designs that do not use TCM (core local SRAM). So you program DMAs input data into its own TCM and work on it from there. GPUs on the other hand hide latencies of memory accesses by switching threads when stalled

dspwizard

6 เดือนที่ผ่านมาdiscuss

TI C2000 is one example

dspwizard

6 เดือนที่ผ่านมาdiscuss

Cadence DSPs have C++17 compatible compiler and will be c++20 soon, new CEVA cores also (both are are clang based). TI C7x is still C++14 (C6000 is ancient core, yet still got c++14 support as you mentioned). AFIR Cadence ASIP generator will give you C++17 toolchain and c++20 is on roadmap, but not 100% sure.

But for those devices you use limited subset of language features and you would be better of not linking c++ stdlib and even c stdlib at all (so junior developers don't have space for doing stupid things ;))

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