Verilog HDL and its ancestors and descendants (2020) [pdf](dl.acm.org)
dl.acm.org
Verilog HDL and its ancestors and descendants (2020) [pdf]
https://dl.acm.org/doi/pdf/10.1145/3386337
7 comments
You had me in the first half. You're absolutely right about the shortcomings of Verilog. I see a lot of similarities between it and PHP - where the language has developed features it doesn't really understand and therefore hasn't quite got right. But it has developed. It goes a fair way to let you do things that otherwise you have to generate code for. And everyone rolls their own code gen. VHDL is vastly inferior at this point in terms of its capabilities especiallly in the verification space, and where Verilog loses in terms of Loose typing it can ameliorated with linting.
The "language wars" narrative feels pretty played-out, so I'm not going to get drawn into it. In the software world everyone seems to recognize that different languages have different strengths, and that there's room for more than one. I'd love to play to the strengths of each language (example: SystemVerilog for verification; VHDL for fixed-point DSP).
A polyglot HDL world is elusive because simulator vendors insist on charging incrementally for language support, and open-source tools fall into either camp Verilog or camp VHDL. This is just another thing to lament.
A polyglot HDL world is elusive because simulator vendors insist on charging incrementally for language support, and open-source tools fall into either camp Verilog or camp VHDL. This is just another thing to lament.
I was an early user of Verilog at MMI/AMD in 1985-88 and attended the first Verilog user group. The article only mentions TEGAS once, but it was a widely used incumbent and the gate-level descriptions in Verilog matched the TEGAS syntax.
See for example https://en.wikipedia.org/wiki/List_of_HDL_simulators
The decision by Synopsys to base their synthesis input on Verilog created an early tipping point to their joint advantage.
The decision by Synopsys to base their synthesis input on Verilog created an early tipping point to their joint advantage.
Verilator is not mentioned!
can someone explain why "pdf" gets a special designation? I understand it's a "document format" and intended for print, but for god sakes why isn't it just as accepted in the browser as HTML? Why hasn't it seamlessly integrated to the point that we don't care anymore?
At least on mobile, it auto-downloads whenever you visit the page. I think it's worth having that be known.
Modern Verilog/SystemVerilog is profoundly hobbled by Verilog's origins as a loosely typed, ad-hoc language (think: Perl, MATLAB, or on an especially rough day, PHP). It has evolved in a committee-and-footgun-rich way reminiscent of C++ - to the point that the article ends by admitting "[i]t is difficult if not impossible for any one engineer to be fluent in the complete language." The language is simultaneously too simple and too complex.
I write VHDL where I can, am hopeful about Clash/Chisel/Lambda, and am optimistic that efforts like CIRCT can replace Verilog in its weird role as machine-produced and machine-digested RTL. In the meantime, though, I don't think Verilog's supremacy is something to be celebrated uncritically.