Dauug|36 will be a 36-bit, 10 MIPS, open-source, maker-constructable minicomputer with preemptive multitasking, paged virtual memory, and no "complex VLSI" (no microprocessor, FPGA, PLD, ASIC, or DRAM). The basic "logic gate" of Dauug|36 is a synchronous static RAM IC (SRAM), which is loaded with a fixed truth table (firmware) at startup, allowing each "gate" to compute any deterministic function of 18 input bits and up to 18 output bits. The CPU is implemented as 22 of these "gates" (read-only SRAMs containing firmware) and some trivial 74AUC glue logic. The instruction set is refreshingly robust and has ~190 opcodes so far.
Dauug|36 will be a 36-bit, 10 MIPS, open-source, maker-constructable minicomputer with preemptive multitasking, paged virtual memory, and no "complex VLSI" (no microprocessor, FPGA, PLD, ASIC, or DRAM). The basic "logic gate" of Dauug|36 is a synchronous static RAM IC (SRAM), which is loaded with a fixed truth table (firmware) at startup, allowing each "gate" to compute any deterministic function of 18 input bits and up to 18 output bits. The CPU is implemented as 22 of these "gates" (read-only SRAMs containing firmware) and some trivial 74AUC glue logic. The instruction set is refreshingly robust and has ~190 opcodes so far.
Dauug|18 will be a simple 18-bit microcontroller also built without "complex VLSI" using the same principles. It's missing a lot relative to Dauug|36: no multitasking, no memory protection, no stack, etc., but only uses 3 SRAM "gates" and 3 more SRAMs for code (2) and data (1) memory.
The download page at 36.dauug.org has an electrical simulation for the 36-bit system (in with the same tarball as everything else). It's slow, since it's designed to catch timing issues. About 23 hours of wall clock time gets 1 CPU second simulated. The RTOS kernel also runs in simulation with preemptive multitasking. It's not ideally packaged because it's not as far along as I would wish.
There is a virtual machine for the 18-bit version, really not ready to release yet due to some gaps, but can be provided to you offline.
Dauug|36 will be a 36-bit, 10 MIPS, open-source, maker-constructable minicomputer with preemptive multitasking, paged virtual memory, and no "complex VLSI" (no microprocessor, FPGA, PLD, ASIC, or DRAM). The basic "logic gate" of Dauug|36 is a synchronous static RAM IC (SRAM), which is loaded with a fixed truth table (firmware) at startup, allowing each "gate" to compute any deterministic function of 18 input bits and up to 18 output bits. The CPU is implemented as 22 of these "gates" (read-only SRAMs containing firmware) and some trivial 74AUC glue logic. The instruction set is refreshingly robust and has ~190 opcodes so far.